With increasing development of central processing units, the processing speeds thereof are progressively increased. For complying with the increasing processing speeds of the central processing units, the collocation of the chipset and the circuit layout of the external main board are sophisticated. Moreover, during transmission of data or commands, any tiny timing difference is critical.
Please refer to FIG. 1, which schematically illustrates a conventional N-bit output circuit of an integrated circuit. Each of the output buffers Bl˜Bn comprises a pull-up unit (PUl˜PUn) and a pull-down unit (PDl˜PDn) coupled to a common power source Vss and a common ground Gnd, respectively. Each of the n-bit input signals bitl˜bitn is inputted into corresponding one of the output buffers Bl˜Bn, respectively, and processed by the pull-up units PUl˜PUn or the pull-down units PDl˜PDn so as to output processed bit signals from output terminals IOl˜IOn. The output terminals IOl˜IOn are connection nodes of the pull-up units PUl˜PUn and the pull-down units PDl˜PDn. Take the output buffer Bl for example. When the first bit signal bitl inputted into the output buffer Bl is at a high level, the pull-up unit PUl is enabled, but the pull-down unit PDl is disabled, thereby outputting a high-level output signal via the output terminal IOl. Whereas, when the first bit signal bitl is at a low level, the pull-up unit PUl is disabled, but the pull-down unit PDl is enabled. Accordingly, it is a low-level output signal outputted via the output terminal IOl. The operation principles of other output buffers are analogous to that of the output buffer Bl, which do not intend to be described redundantly herein.
Since all of the output buffers Bl˜Bn are electrically connected to the common power source Vss and the common ground Gnd, a so-called SSO skew phenomenon is suffered from. Generally, when the state of the output terminal of an output buffer is switching, power/ground bounce noise is derived from the flow of intense current through an equivalent parasitic inductance associated with bonding wires, lead frames and pins.
When the output terminals of a number of output buffers simultaneously change their output states from a low level to a high level or from a high level to a low level, the SSO skew phenomenon is likely to occur. Further, when the count of the output terminals on changing from the high level to the low level is much higher or lower than the count of the output terminals on changing from the low level to the high level at the same time, the SSO skew becomes more serious.
As shown in FIG. 2(a), when the number of output buffers changing from the high level to the low level and the number of output buffers changing from the low level to the high level at the same time are equal to each other, the SSO skew is minimal. It is because the period when the output terminals change from the high level to the low level (curve A) and the period when the output terminals change from the low level to the high level (curve B) are substantially coincident.
Referring to FIG. 2(b), a case that the number of output terminals changing from the high level to the low level is less than the number of output terminals changing from the low level to the high level is illustrated. Since the number of the output terminals on changing from the low level to the high level is increased compared to the case shown in FIG. 2(a), the complete state change of the output terminals from the low level to the high level (curve B′) delays with a time period Δt1, compared with curve B. On the other hand, since the number of the output terminals on changing from the high level to the low level is less than that in FIG. 2(a), the state change of the output terminals indicated by curve A′ occurs in advance compared to curve A with a time period Δt3. The opposite shifts of the state change timing enlarge the SSO skew. The delay time Δt1 and the advancing time Δt3 will increase and thus the SSO skew will be even serious when the number of the output terminals changing from the low level to the high level is even larger than the other.
Likewise, referring to FIG. 2(c), a case that the number of output terminals changing from the high level to the low level is larger than the number of output terminals changing from the low level to the high level is illustrated. Since the number of the output terminals on changing from the high level to the low level is increased compared to the case shown in FIG. 2(a), the complete state change of the output terminals from the high level to the low level (curve B″) delays with a time period Δt2, compared with curve B. On the other hand, since the number of the output terminals on changing from the low level to the high level is less than that in FIG. 2(a), the state change of the output terminals indicated by curve A″ occurs in advance compared to curve A with a time period Δt4. The opposite shifts of the state change timing also enlarge the SSO skew. The delay time Δt2 and the advancing time Δt4 will increase and thus the SSO skew will be even serious when the number of the output terminals changing from the low level to the high level is even larger than the other.
When the buses connected to the output terminals of the output buffers operate at a low speed, the SSO skew phenomenon can be neglected. However, with the increasing operating speeds of the buses, even the tiny timing difference resulting from SSO skew may cause erroneous data access or breakdown of the overall computer system.